1. Field of the Invention
This invention relates to semiconductor memory and, more particularly, to systems and methods for improving the performance of a flash memory device, while maintaining high reliability.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Numerous types of semiconductor memory are currently available in the marketplace today. Though an array of storage elements is commonly included within each type of memory, the storage elements of different memory types often differ in both architecture and function. For example, a memory storage element can be volatile or non-volatile. Types of volatile memory include memory that must be periodically refreshed (e.g., DRAM) or memory that will lose its programmed state if power is removed from the memory circuit (e.g., SRAM). Unlike volatile memory, however, non-volatile memory is able to maintain its stored contents when power is removed from the memory circuit. Types of non-volatile memory include read-only memory (such as ROM, PROM, EPROM and EEPROM), magnetic random access memory (MRAM), battery-backed SRAM (BBSRAM) and flash memory.
There are two primary types of flash memory technologies—NOR flash and NAND flash. NOR flash is commonly used in embedded core applications, whereas NAND flash is commonly used to replace bulk storage. Like most semiconductor memory, each flash memory device may generally include an array of storage elements or memory cells. However, the storage elements included within NOR and NAND flash devices differ in both architecture and function, and therefore, provide different advantages/disadvantages.
For example, NOR technology features high-speed, random access to bit storage, low error rates and high endurance (e.g., it may support up to one million program/erase cycles without requiring error correction). However, because the memory cells of a NOR flash device are each coupled in parallel between a common bit line and individual source lines, NOR technology offers less density (and therefore, higher cost) than NAND flash devices. NOR flash devices also tend to consume more power and require a longer programming time than NAND flash devices. On the other hand, NAND technology ties a string of single-bit storage transistors (constituting, e.g., 16 or 32 memory cells) in series between a common bit line and a common source line. This reduces the number of memory cell contacts and allows greater density. However, because the memory cells must be accessed sequentially, read and write errors tend to be more prevalent in NAND flash devices. As a result, NAND devices require error correction.
A commonality between all flash devices is that a memory cell must be erased before data can be programmed (or written to) a memory cell. Though each device can be erased on a block-basis, the reading and programming times for a NAND flash device are significantly shorter than those of a NOR flash device (sometimes by an order of magnitude). For example, the programming current is very small in NAND flash devices, which use Fowler-Nordheim tunneling for both erasing and programming. Because the programming current is very small, the power consumption for programming does not significantly increase when the number of memory cells being programmed is increased. This allows a plurality of NAND flash memory cells to be programmed at the same time, so that the programming time per byte becomes very short. In most cases, the read and program operations of a NAND flash device take place on a page-basis (e.g., 528 bytes at a time for most NAND devices). Since NOR flash devices use the hot electron injection mechanism for programming, they tend to consume more power and require significantly longer programming times per byte than NAND flash devices. For example, most NOR flash devices can only be programmed one byte or word at a time.
Since NAND flash devices are subject to data failures (i.e., errors) that occur during device operation, system error-checking and correction algorithms are often implemented to ensure data read/write integrity. For example, error correction code (ECC) algorithms may be included within an externally-located flash memory controller to ensure that the data programmed to a memory cell is the same data read from the memory cell. To perform error correction, the data read from the memory cell is copied to an external memory controller having an ECC unit. The ECC unit determines whether the ECC code stored along with the data when it was programmed to a memory cell is identical to the ECC code calculated when the stored data is read. If a difference exists, the erroneous data is corrected or changed to its previously stored state.
Though system error-checking and correction algorithms improve reliability (by checking for and correcting errors in stored data), they tend to reduce the performance of NAND flash devices by transferring the data outside of the memory array to an external memory controller. This often increases the read and write times of the flash memory device. Therefore, a need remains for improved flash memory devices and methods for improving the read/write performance of a flash memory device while also maintaining high reliability.